? semiconductor components industries, llc, 2001 october, 2001 rev. 7 1 publication order number: sn74ls221/d sn74ls221 dual monostable multivibrators with schmitt-trigger inputs each multivibrator of the ls221 features a negative-transition- triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. schmitt-trigger input circuitry for b input allows jitter-free triggering for inputs as slow as 1 volt/second, providing the circuit with excellent noise immunity. a high immunity to v cc noise is also provided by internal latching circuitry. once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. the output pulses can be terminated by the overriding clear. input pulse width may be of any duration relative to the output pulse width. output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. with r ext = 2.0 k w and c ext = 0, a typical output pulse of 30 nanoseconds is achieved. output rise and fall times are independent of pulse length. pulse width stability is achieved through internal compensation and is virtually independent of v cc and temperature. in most applications, pulse stability will only be limited by the accuracy of external timing components. jitter-free operation is maintained over the full temperature and v cc ranges for greater than six decades of timing capacitance (10 pf to 10 m f), and greater than one decade of timing resistance (2.0 to 100 k w for the sn74ls221). pulse width is defined by the relationship: t w (out) = c ext r ext ln 2.0 0.7 c ext r ext ; where t w is in ns if c ext is in pf and r ext is in k w . if pulse cutoff is not critical, capacitance up to 1000 m f and resistance as low as 1.4 k w may be used. the range of jitter-free pulse widths is extended if v cc is 5.0 v and 25 c temperature. ? sn74ls221 is a dual highly stable one-shot ? overriding clear terminates output pulse ? pin out is identical to sn74ls123 guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky soic d suffix case 751b plastic n suffix case 648 16 1 16 1 device package shipping ordering information sn74ls221n 16 pin dip 2000 units/box sn74ls221d soic16 38 units/rail sn74ls221dr2 soic16 2500/tape & reel http://onsemi.com
sn74ls221 http://onsemi.com 2 (top view) positive logic: low input to clear resets q low and positive logic: q high regardless of dc levels at a positive logic: or b inputs. 14 13 12 11 10 9 123456 7 16 15 8 v cc 1a 1 r ext/ c ext 1 c ext 1q 2q 2b 2 clr 2a 1b 1 clr 1q 2q 2 c ext 2 r ext / c ext gnd q q clr q q clr + v cc r ext r/c c ext function table (each monostable) inputs outputs clear a b q q l x x l h x h xl h x x ll h h l h h * l h *see operational notes e pulse trigger modes type typical power maximum output pulse dissipation length sn74ls221 23 mw 70 s
sn74ls221 http://onsemi.com 3 operational notes once in the pulse trigger mode, the output pulse width is determined by t w = r ext c ext in2, as long as r ext and c ext are within their minimum and maximum valves and the duty cycle is less than 50%. this pulse width is essentially independent of v cc and temperature variations. output pulse widths varies typically no more than 0.5% from device to device. if the duty cycle, defined as being 100 t w t where t is the period of the input pulse, rises above 50%, the output pulse width will become shorter. if the duty cycle varies between low and high valves, this causes the output pulse width to vary in length, or jitter. to reduce jitter to a minimum, r ext should be as large as possible. (jitter is independent of c ext ). with r ext = 100k, jitter is not appreciable until the duty cycle approaches 90%. although the ls221 is pin-for-pin compatible with the ls123, it should be remembered that they are not functionally identical. the ls123 is retriggerable so that the output is dependent upon the input transitions once it is high. this is not the case for the ls221. also note that it is recommended to externally ground the ls123 c ext pin. however, this cannot be done on the ls221. the sn74ls221 is a dual, monolithic, non-retriggerable, high-stability one shot. the output pulse width, t w can be varied over 9 decades of timing by proper selection of the external timing components, r ext and c ext . pulse triggering occurs at a voltage level and is, therefore, independent of the input slew rate. although all three inputs have this schmitt-trigger effect, only the b input should be used for very long transition triggers ( 1.0 m v/s). high immunity to v cc noise (typically 1.5 v) is achieved by internal latching circuitry. however, standard v cc bypassing is strongly recommended. the ls221 has four basic modes of operation. clear mode: if the clear input is held low, irregardless of the previous output state and other input states, the q output is low. inhib- it mode: if either the a input is high or the b input is low, once the q output goes low, it cannot be retriggered by other inputs. pulse trigger mode: a transition of the a or b inputs as indicated in the functional truth table will trigger the q output to go high for a duration determined by the t w equation described above; q will go low for a corresponding length of time. the clear input may also be used to trigger an output pulse, but special logic precondi- tioning on the a or b inputs must be done as follows: following any output triggering action using the a or b inputs, the a input must be set high or the b input must be set low to allow clear to be used as a trigger. inputs should then be set up per the truth table (without triggering the output) to allow clear to be used a trigger for the output pulse. if the clear pin is routinely being used to trigger the output pulse, the a or b inputs must be toggled as described above before and between each clear trigger event. once triggered, as long as the output remains high, all input transitions (except overriding clear) are ignored. overriding clear mode: if the q output is high, it may be forced low by bringing the clear input low.
sn74ls221 http://onsemi.com 4 dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v t+ positive-going threshold voltage at c input 1.0 2.0 v v cc = min v t negative-going threshold voltage at c input 0.7 0.8 v v cc = min v t+ positive-going threshold voltage at b input 1.0 2.0 v v cc = min v t negative-going threshold voltage at b input 0.8 0.9 v v cc = min v ih input high voltage 2.0 v guaranteed input high voltage for a input v il input low voltage 0.8 v guaranteed input low voltage for a input v ik input clamp voltage 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.4 v v cc = min, i oh = max v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v cc = min i ih in p ut high current 20 m a v cc = max, v in = 2.7 v i ih input high current 0.1 ma v cc = max, v in = 7.0 v i il input low current input a input b clear 0.4 0.8 0.8 ma v cc = max, v in = 0.4 v i os short circuit current (note 1) 20 100 ma v cc = max i cc power supply current quiescent 4.7 11 ma v cc = max i cc triggered 19 27 ma v cc = max note 1: not more than one output should be shorted at a time, nor for more than 1 second.
sn74ls221 http://onsemi.com 5 ac characteristics (v cc = 5.0 v, t a = 25 c) from to limits symbol f rom (input) t o (output) min typ max unit test conditions t plh a q 45 70 ns t plh b q 35 55 ns t phl a q 50 80 ns c t =80 p fr t =20 w t phl b q 40 65 ns c ext = 80 pf, r ext = 2.0 w t phl clear q 35 55 ns c l = 15 pf, t plh clear q 44 65 ns c l = 15 f , see figure 1 70 120 150 c ext = 80 pf, r ext = 2.0 w t w( t) aorb qorq 20 47 70 ns c ext = 0, r ext = 2.0 k w t w(out) a or b q or q 600 670 750 c ext = 100 pf, r ext = 10 k w 6.0 6.9 7.5 ms c ext = 1.0 m f, r ext = 10 k w ac setup requirements (v cc = 5.0 v, t a = 25 c) limits symbol parameter min typ max unit rate of rise or fall of input pulse dv/dt schmitt, b 1.0 v/s dv/dt logic input, a 1.0 v/ m s input pulse width t w a or b, t w(in) 40 ns t w clear, t w (clear) 40 t s clear-inactive-state setup time 15 ns r ext external timing resistance 1.4 100 k w c ext external timing capacitance 0 1000 m f output duty cycle rt = 2.0 k w 50 % r t = max r ext 90
sn74ls221 http://onsemi.com 6 ac waveforms b input clear q output q output a input is low. b input clear q output a input is low. b input clear q output a input is low. t w(in) 60 ns t plh t phl t plh t phl 1.3 v 3 v 0 v 3 v 0 v v oh v ol v oh v ol 60 ns 1.3 v 1.3 v 3 v 0 v 3 v 0 v v oh v ol 50 ns 0 t s 3 v 0 v 3 v 0 v v oh v ol 3 v 0 v 3 v 0 v v oh v ol triggered not triggered 50 ns 50 ns b input clear q output a input is low. t w(out) trigger from b, then clear e condition 1 trigger from b, then clear e condition 2 clear overriding b, then trigger from b triggering from positive transition of clear figure 1.
sn74ls221 http://onsemi.com 7 package dimensions n suffix plastic package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
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